The present invention relates to a field effect transistor having an extremely short channel length.
Transistors of this general kind are known, for example, from the technical publication, "IEEE Journal of Solid-State Circuits", Vol. SC-14 10, No. 5, Oct. 1975, pp. 322-331. In order to achieve a high "punch-through voltage" which is defined as that value of the drain voltage at which the drain-side depletion zones reaches the source zone, and in order to simultaneously avoid the drain voltage noticeably influencing the transistor internal resistance, the transistors described in this publication are designed as so-called DMOS field effect transistors which is to be understood as a MOS-transistor structure obtained by a double-diffusion technique. Here the source and drain zones are diffused into the surface of a doped semiconductor layer at a normal spacing, although this diffusion process is preceded by another in which, in the source zone, there is formed a diffusion trough which considerably reinforces the doping of the semiconductor layer and into which the source zone is then diffused.
In the DMOS-technique, a transistor channel is formed, the main part of which runs between the edge of the diffusion trough and the edge of the drain zone, whereas only a very small part thereof lies between the edge of the diffusion trough and the edge of the source zone embedded in the latter. This latter part determines the effective channel length of the transistor within which the charge carrier transportation is controlled by means of a gate electrode insulated from the semiconductor surface and a control voltage supplied to this gate electrode, whereas the punch-through voltage assumes values which also occur in MOS-transistors having a channel length which corresponds to the source-drain interval.
However, in field effect transistors produced in the DMOS-technique, the disadvantage occurs that the effective channel length is dependent upon the course of the double-diffusion process. As generally speaking, a plurality of similar transistors, which in particular are arranged on a common substrate, are simultaneously subjected to this process, the effective channel lengths and the saturation voltages of all these transistors--the latter assuming equal gate voltages--are identical to one another or at least have a process-dependent relationship to one another.